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ARMv7 Generic Timers: Difference between revisions
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This page is current with the description of the ARM Generic Timer behaviour specified in the ARMv7 manual. There may have been differences introduced in ARMv8 and AArch64. This page does not take such differences, if they exist, into account.
This page is meant to be a quick reference and refresher on the way the ARMv7 generic timers work.
= Overview =
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* The timers can operate in either physical or virtual time.
* The timers output signals can be configured as level-sensitive PPI IRQ signals to the GICC.
== Security Extentions not implemented ==
* Physical timer and virtual timer.
The virtual timer should be used by PL1 kernels. The physical timer should ideally be left alone.
== Security extensions implemented, no Hypervisor extensions implemented ==
* '''non-secure''' physical timer.
* '''Secure''' physical timer.
* Virtual timer.
The virtual timer should be used by non-secure PL1 kernels.
The secure physical timer should be used by PL3 monitors and '''secure''' PL1 kernels.
The non-secure physical timer should be ideally left alone, and seems to exist solely for the sake of supporting non-secure PL1 kernels which insist on using the physcounter and physical registers instead of the virtcounter and virtual registers.
== Security extensions and hypervisor extensions implemented ==
* '''Non-secure''' PL1 physical timer.
* '''Secure''' PL1 physical timer.
* '''Non-secure''' PL2 physical timer.
* Virtual timer.
The virtual timer should be used by non-secure PL1 kernels.
The secure PL1 physical timer should be used by '''secure''' PL1 kernels.
The '''non-secure''' PL2 physical timer should be used by PL2 hypervisors.
The '''non-secure''' PL1 physical timer should be left alone, ideally and seems to exist solely for the sake of supporting non-secure PL1 kernels that insist on using the physcounter and physical registers instead of the virtcounter and virtual registers.
== Registers ==
{{stub|section=y}}
== CNTFREQ ==
{{stub|section=y}}
[[Category:ARM]]
[[Category:Timers]]
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