ARMv7 Common Memory System Architecture: Difference between revisions
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In ARM processors, the instruction and data/unified caches can be separately enabled and disabled. The Data/unified cache(s) are enabled as a group, and the instruction cache(s) are separately enabled as their own group. ARMv7 provides a way for software to reason about caches in a uniform manner across implementations. Prior to ARMv7, ARM only architecturally specified one level of cache and support for and management of all other levels of cache was <IMPLEMENTATION DEFINED>. ARMv7 introduces the concepts of '''Level of Unification''' and '''Level of Coherency''' in order for software to interact robustly with diverse caches.
====Level of Unification (verbatim)====
The PoU for a processor is the point by which the instruction and data caches and the translation table walks of that processor are guaranteed to see the same copy of a memory location. In many cases, the point of unification is the point in a uniprocessor memory system by which the instruction and data caches and the translation table walks have merged. The PoU for an Inner Shareable shareability domain is the point by which the instruction and data caches and the translation table walks of all the processors in that Inner Shareable shareability domain are guaranteed to see the same copy of a memory location.Defining this point permits self-modifying software to ensure future instruction fetches are associated with the modified version of the software by using the standard correctness policy of:
* Clean data cache entry by address.
====Level of Coherency====▼
* Invalidate instruction cache entry by address.
The PoU also permits a uniprocessor system that does not implement the Multiprocessing Extensions to use the clean data cache entry operation to ensure that all writes to the translation tables are visible to the translation table walk hardware.
▲====Level of Coherency (verbatim)====
For a particular MVA, the PoC is the point at which all agents that can access memory are
guaranteed to see the same copy of a memory location. In many cases, this is effectively the main
system memory, although the architecture does not prohibit the implementation of caches beyond
the PoC that have no effect on the coherence between memory system agents.
===Enumerating processor-controlled caches===
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