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ARM SMMU versions 1 and 2: Difference between revisions
→Secure/Non-secure mode split and SSD
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** When the SSD space is present in the SMMU, the SMMU_SSDRn registers are present.
** These SMMU_SSDRn registers are bitfields, 32 bits each. If bit<N> is 1 then device<N> is non-secure, else it is secure.
==== Splitting the Stream Mapping table between secure and non-secure mode ====
The Stream Mapping table is global and shared between Secure and non-secure mode. Secure mode must decide how many Stream Mapping register groups it will expose for non-secure mode's use. ARM recommends that secure mode software leaves at least one Stream mapping register group for use by non-secure software.
Having an SMMU_S2CR which has been allocated to secure be configured to mode point to a context bank which is non-secure is UNPREDICTABLE. Having an SMMU_S2CR which has been allocated to non-secure mode be configured to point to a context bank which is secure will trigger an Unimplemented Context Bank SMMU Fault
==== Splitting the Context banks between secure and non-secure mode ====
Some number of context banks can be reserved for use by secure mode using SMMU_SCR1.NSNUMSBO. The allocation begins from the top of the available context bank space. The SMMU will intelligently present the correct number of context banks to non-secure mode through non-secure accesses to SMMU_IDR1.NUMCB.
=== Translation, bypass and faulting ===
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