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ARM SMMU versions 1 and 2: Difference between revisions
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== Terminology: ==
* Just in general, the SMMU spec refers to DMA engines and MCUs on the chipset as being "upstream" from the SMMU and it refers to RAM as being "downstream" from the SMMU.
* The "Stream mapping table" is a term used to refer to the combined working of the SMMU_SMRn + SMMU_S2CRn registers. Do not confuse the SMMU_SMRn ("Stream ''match''ing registers") with the umbrella term "Stream ''mapp''ing registers". ARM defines Stream mapping as (Section 2.3.2) "''the process of mapping a StreamID to the associated Stream-to-Context register,
SMMU_S2CRn''".
* "Contexts" are synonymous with Intel's "domain" terminology used in the VT-d specification; they refer to a set of IO-page tables for translating IO-Addresses into output addresses on the bus/memory controller.
* Transactions: Any write to or read from the SMMU by any agent is an SMMU transaction.
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''ARM found it important to mention that if the SMMU support Extended Stream Matching and the extension is not enabled, the (up to) 128 SMMU_SMRs that are exposed, map onto the final 128 SMMU_SMRs provided by the extension. Since it's apparently important, I'll mention it too.''
=== Number of supported Contexts ===
The max number of supported contexts is implied by the max number of SMMU_S2CRn registers.
* Multiple SMMU_SMRn regs may cause multiple StreamIDs to map to the same Context when Stream Matching is used.
* Each incoming StreamID maps directly to a specific Context when Stream Indexing is used.
== Client transaction flowchart ==
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