ARM SMMU versions 1 and 2: Difference between revisions

ARM SMMU versions 1 and 2 (view source)

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Revision as of 04:55, 3 April 2019 (view source) osdev>Gravaera m (→‎Setup/Initialization related information) ← Older edit		Latest revision as of 03:50, 8 August 2019 (view source) osdev>Gravaera m (Categorize)
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Line 96: * Support for Stream Matching is indicated via SMMU_IDR0.SMS == 1. * Support for Extended Stream Matching is indicated via SMMU_IDR0.EXSMRGS == 1. * Enable Extended Stream Matching using SMMU_sCR2.EXSMRGENABLE==1. ** Setting SMMU_SCR2.EXNSSMRGDISABLE==1 with a secure write to SMMU_SCR2 disables the use of Extended Stream Matching by non-secure mode. * Support for compressed Indexing (which is a subfeature under Stream Matching) is indicated via a secure read of SMMU_IDR2.COMPINDEXS == 1. A non-secure read of this bit only states whether or not compressed indexing is available for use by non-secure software. * The number of Stream Mapping Register Groups is determined by reading SMMU_IDR0.NUMSMRG. Line 277 ⟶ 279: * For SMMUv1, the SMMU_CBAR register states which interrupt is raised to signal faults while processing that context. * For SMMUv2, each context bank has its own IRQ pin. [[Category:ARM]]