ARM Paging: Difference between revisions

=== Overview ===

Detecting paging support is done by consulting the "coprocessor" registers. It is represented in ID_MMFR0

mcr p15, 0, <Rt>, c0, c1, 4

The structure of the register is as follows:

{| class="wikitable"

* PD1 - like EPD1.

* PD0 - like EPD0.

* T0SZ - like T1SZ. If EAE=0, this is field N.

* N - Indicated the width of the base address in TTBR0. The base address is bits [31:14-N]. If N=0, the format is compatible with ARMv5 and ARMv6. This field also determines whether TTBR0 or TTBR1 is used for the page walk.

To access TTBCR, software reads or writes the CP15 registers with <opc1> set to 0, <CRn> set to c2, <CRm> set to c0,

and <opc2> set to 2. For example:

MRC p15, 0, <Rt>, c2, c0, 2 ; Read TTBCR into Rt

MCR p15, 0, <Rt>, c2, c0, 2 ; Write RT to TTBCR

(ARMv7-A ARM, Section B4.1, page 1728)<br />

Here RT denotes a register of your choice.

of TTBR0 in an implementation that includes the Large Physical Address Extension, software reads or writes the

CP15 registers with <opc1> set to 0, <CRn> set to c2, <CRm> set to c0, and <opc2> set to 0. For example:

MRC p15, 0, <Rt>, c2, c0, 0 ; Read 32-bit TTBR0 into Rt

MCR p15, 0, <Rt>, c2, c0, 0 ; Write Rt to 32-bit TTBR0

In an implementation that includes the Large Physical Address Extension, to access all 64 bits of TTBR0, software

performs a 64-bit read or write of the CP15 registers with <CRm> set to c2 and <opc1> set to 0. For example:

MRRC p15, 0, <Rt>, <Rt2>, c2 ; Read 64-bit TTBR0 into Rt (low word) and Rt2 (high word)

MCRR p15, 0, <Rt>, <Rt2>, c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR0

In these MRRC and MCRR instructions, Rt holds the least-significant word of TTBR0, and Rt2 holds the most-significant

word.

of TTBR1 in an implementation that includes the Large Physical Address Extension, software reads or writes the

CP15 registers with <opc1> set to 0, <CRn> set to c2, <CRm> set to c0, and <opc2> set to 1. For example:

MRC p15, 0, <Rt>, c2, c0, 1 ; Read 32-bit TTBR1 into Rt

MCR p15, 0, <Rt>, c2, c0, 1 ; Write Rt to 32-bit TTBR1

In an implementation that includes the Large Physical Address Extension, to access all 64 bits of TTBR1, software

performs a 64-bit read or write of the CP15 registers with <CRm> set to c2 and <opc1> set to 1. For example:

MRRC p15, 1, <Rt>, <Rt2>, c2 ; Read 64-bit TTBR1 into Rt (low word) and Rt2 (high word)

MCRR p15, 1, <Rt>, <Rt2>, c2 ; Write Rt (low word) and Rt2 (high word) to 64-bit TTBR1

In these MRRC and MCRR instructions, Rt holds the least-significant word of TTBR1, and Rt2 holds the most-significant

word.

 

[[Category:ARM]]

[[Category:Memory management]]