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APIC: Difference between revisions
Added table of LAPIC registers. Table taken from the x86 sdm (Volume 3A, Chapter 10.4)
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(Added table of LAPIC registers. Table taken from the x86 sdm (Volume 3A, Chapter 10.4)) |
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== Local APIC registers ==
The local APIC registers are memory mapped to an address that can be found in the MP/MADT tables. Make sure you map these to virtual memory if you are using paging. Each register is 32 bits long, and expects to be written and read as a 32 bit integer. Although each register is 4 bytes, they are all aligned on a 16 byte boundary.
List of local APIC registers (TODO: Add descriptions for all registers):
{| {{wikitable}}
|-
| Offset
| Register name
| Read/Write permissions
|-
|-
| 000h - 010h
| Reserved
|
|-
|-
| 020h
| LAPIC ID Register
| Read/Write
|-
|-
| 030h
| LAPIC Version Register
| Read only
|-
|-
| 040h - 070h
| Reserved
|
|-
|-
| 080h
| Task Priority Register (TPR)
| Read/Write
|-
|-
| 090h
| Arbitration Priority Register (APR)
| Read only
|-
|-
| 0A0h
| Processor Priority Register (PPR)
| Read only
|-
|-
| 0B0h
| EOI register
| Write only
|-
|-
| 0C0h
| Remote Read Register (RRD)
| Read only
|-
|-
| 0D0h
| Logical Destination Register
| Read/Write
|-
|-
| 0E0h
| Destination Format Register
| Read/Write
|-
|-
| 0F0h
| Spurious Interrupt Vector Register
| Read/Write
|-
|-
| 100h - 170h
| In-Service Register (ISR)
| Read only
|-
|-
| 180h - 1F0h
| Trigger Mode Register (TMR)
| Read only
|-
|-
| 200h - 270h
| Interrupt Request Register (IRR)
| Read only
|-
|-
| 280h
| Error Status Register
| Read only
|-
|-
| 290h - 2E0h
| Reserved
|
|-
|-
| 2F0h
| LVT Corrected Machine Check Interrupt (CMCI) Register
| Read/Write
|-
|-
| 300h - 310h
| Interrupt Command Register (ICR)
| Read/Write
|-
|-
| 320h
| LVT Timer Register
| Read/Write
|-
|-
| 330h
| LVT Thermal Sensor Register
| Read/Write
|-
|-
| 340h
| LVT Performance Monitoring Counters Register
| Read/Write
|-
|-
| 350h
| LVT LINT0 Register
| Read/Write
|-
|-
| 360h
| LVT LINT1 Register
| Read/Write
|-
|-
| 370h
| LVT Error Register
| Read/Write
|-
|-
| 380h
| Initial Count Register (for Timer)
| Read/Write
|-
|-
| 390h
| Current Count Register (for Timer)
| Read only
|-
|-
| 3A0h - 3D0h
| Reserved
|
|-
|-
| 3E0h
| Divide Configuration Register (for Timer)
| Read/Write
|-
|-
| 3F0h
| Reserved
|
|-
|}
=== EOI Register ===
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* [http://developer.intel.com/design/chipsets/specupdt/290710.htm updated I/O APIC specification/datasheet]
* [http://www.intel.com/products/processor/manuals/ Volume 3A:System Programming Guide, Part 1,manuals has a chapter on the APIC]
* [http://www.intel.com/products/processor/manuals/ Volume 3A:System Programming Guide, Chapter 10.4 for further reading about the LAPIC]
* [http://web.archive.org/web/20140308064246/http://www.osdever.net/tutorials/pdf/apic.pdf Advanced Programmable Interrupt Controller by Mike Rieker]
* [http://web.archive.org/web/20100918084750/http://www.microsoft.com/whdc/archive/apic.mspx "The Importance of Implementing APIC-Based Interrupt Subsystems on Uniprocessor PCs". Microsoft. 18 September 2010]
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