APIC: Difference between revisions

The local APIC registers are memory mapped to an address that can be found in the MP/MADT tables. Make sure you map these to virtual memory if you are using paging. Each register is 32 bits long, and expects to be written and read as a 32 bit integer. Although each register is 4 bytes, they are all aligned on a 16 byte boundary. (TODO: Complete the list of registers)

Write to the register with offset 0xB0 using the value 0 to signal an end of interrupt. A non-zero valuesvalue causes a general protection fault.

| BitBits 8-11 (reserved for timer)

| Destination type. If this is > 0 then the destination field in 0x310 is ignored. 1 will always send the interrupt to the itself, 2 will send it to all processors, and 3 will send it to all processors aside from the current one. It is best to avoid using modes 1, 2 and 3, and stick with 0.

IOAPICBASE+0x10. All accesses must be done on uint32_t4 byte boundaries. The address register uses the bottom 8 bits for register select. Here is some example code that illustrates this:

The redirection table allows you to choose which externel interrupts are sent to which processors and with which interrupt vectors. When choosing the processors you should consider: spreading out the workload between the processors, avoiding processors in a low-power state, avoiding throttled processors. When choosing the interrupt vectors you should remember that interrupts 0x00 to 0x1F are reserved for internal processor exceptions, the interrupts you remaped the PIC to may receive spurious interrupts, that 0xFF is probably where you put the APIC spurious interrupt, and that the upper 4 bits of aan interrupt vector indicate its priority.