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m →‎EOI Register: Clarify that it may not #GP
the 14th and 15th Interrupt Command Register bits have been mixed up; see Volume 3A:System Programming Guide, Chapter 10.6.1
Line 314:
|-
| Bit 14
| Level. 0 = De-assert, 1 = Assert (only 1 for INIT de-assert)
| Clear for INIT level de-assert, otherwise set.
|-
| Bit 15
| SetTrigger Mode. 0 = Edge, 1 = Level (only 1 for INIT levelassert and de-assert, otherwise clear.)
|-
| Bits 18-19
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