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APIC: Difference between revisions

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Code style fix (no softians or javanians here)
Line 42:
* note that this requires CPUID to be supported.
*/
bool cpuHasAPICcheck_apic() {
{
uint32_t eax, edx;
cpuid(1, &eax, &edx);
Line 50 ⟶ 49:
 
/* Set the physical address for local APIC registers */
void cpuSetAPICBasecpu_set_apic_base(uintptr_t apic) {
{
uint32_t edx = 0;
uint32_t eax = (apic & 0xfffff100) | IA32_APIC_BASE_MSR_ENABLE;
Line 59 ⟶ 57:
#endif
 
cpuSetMSRcpu_set_msr(IA32_APIC_BASE_MSR, eax, edx);
}
 
Line 66 ⟶ 64:
* make sure you map it to virtual memory ;)
*/
uintptr_t cpuGetAPICBasecpu_get_acpi_base() {
{
uint32_t eax, edx;
cpuGetMSRcpu_get_msr(IA32_APIC_BASE_MSR, &eax, &edx);
 
#ifdef __PHYSICAL_MEMORY_EXTENSION__
Line 78 ⟶ 75:
}
 
void enableAPICenable_apic() {
{
/* Hardware enable the Local APIC if it wasn't enabled */
cpuSetAPICBasecpu_set_apic_base(cpuGetAPICBase());
 
/* Set the Spourious Interrupt Vector Register bit 8 to start receiving interrupts */
WriteRegisterwrite_reg(0xF0, ReadRegister(0xF0) | 0x100);
}
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