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== Introduction ==
 
AHCI (Advance Host Controller Interface) is developed by Intel to facilitate handling [[SATA]] devices. The AHCI specification emphasizes that an AHCI controller (referred to as host bus adapter, or HBA) is designed to be a data movement engine between system memory and SATA devices. It encapsulates SATA devices and provides a standard [[PCI]] interface to the host. System designers can easily access SATA drives using system memory and memory mapped registers, without the need for manipulating the annoying task files as IDE do.
 
An AHCI controller may support up to 32 ports which can attach different SATA devices such as disk drives, port multipliers, or an enclosure management bridge. AHCI supports all native SATA features such as command queueing, hot plugging, power management, etc. To a software developer, an AHCI controller is just a PCI device with bus master capability.
 
AHCI is a new standard compared to [[IDE]], which has been around for twenty years. There exists little documentation about its programming tips and tricks. Possibly the only available resource is the Intel AHCI specification (see [[#External Links|External Links]]) and some open source operating systems such as Linux. This article shows the minimal steps an OS (not BIOS) should do to put AHCI controller into a workable state, how to identify drives attached, and how to read physical sectors from a SATA disk. To keep concise, many technical details and deep explanations of some data structures have been omitted.
 
It should be noted that IDE also supports SATA devices and there are still debates about which one, IDE or AHCI, is better. Some tests even show that a SATA disk acts better in IDE mode than AHCI mode. But the common idea is that AHCI performs better and will be the standard PC to SATA interface, though some driver software should be enhanced to fully cultivate AHCI capability.
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Following code defines different kinds of FIS specified in Serial ATA Revision 3.0.
 
<sourcesyntaxhighlight lang="c">
typedef enum
{
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FIS_TYPE_DEV_BITS = 0xA1, // Set device bits FIS - device to host
} FIS_TYPE;
</syntaxhighlight>
</source>
 
'''2) Register FIS – Host to Device'''
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A host to device register FIS is used by the host to send command or control to a device. As illustrated in the following data structure, it contains the IDE registers such as command, LBA, device, feature, count and control. An ATA command is constructed in this structure and issued to the device. All reserved fields in an FIS should be cleared to zero.
 
<sourcesyntaxhighlight lang="c">
typedef struct tagFIS_REG_H2D
{
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uint8_t rsv1[4]; // Reserved
} FIS_REG_H2D;
</syntaxhighlight>
</source>
 
'''3) Register FIS – Device to Host'''
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A device to host register FIS is used by the device to notify the host that some ATA register has changed. It contains the updated task files such as status, error and other registers.
 
<sourcesyntaxhighlight lang="c">
typedef struct tagFIS_REG_D2H
{
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uint8_t rsv4[4]; // Reserved
} FIS_REG_D2H;
</syntaxhighlight>
</source>
 
'''4) Data FIS – Bidirectional'''
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This FIS is used by the host or device to send data payload. The data size can be varied.
 
<sourcesyntaxhighlight lang="c">
typedef struct tagFIS_DATA
{
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uint32_t data[1]; // Payload
} FIS_DATA;
</syntaxhighlight>
</source>
 
'''5) PIO Setup – Device to Host'''
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This FIS is used by the device to tell the host that it’s about to send or ready to receive a PIO data payload.
 
<sourcesyntaxhighlight lang="c">
typedef struct tagFIS_PIO_SETUP
{
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uint8_t rsv4[2]; // Reserved
} FIS_PIO_SETUP;
</syntaxhighlight>
</source>
 
'''6) DMA Setup – Device to Host'''
 
<sourcesyntaxhighlight lang="c">
typedef struct tagFIS_DMA_SETUP
{
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//DWORD 1&2
 
uint64_t DMAbufferID; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
// SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
 
//DWORD 3
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} FIS_DMA_SETUP;
</syntaxhighlight>
</source>
 
'''7) Example'''
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To issue an ATA Identify command to the device, the FIS is constructed at follows.
 
<sourcesyntaxhighlight lang="c">
FIS_REG_H2D fis;
memset(&fis, 0, sizeof(FIS_REG_H2D));
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fis.device = 0; // Master device
fis.c = 1; // Write command register
</syntaxhighlight>
</source>
 
After the device receives this FIS and successfully read the 256 words data into its internal buffer, it sends a PIO Setup FIS – Device to Host to tell the host that it’s ready to transfer data and the data size (FIS_PIO_SETUP.tc).
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== Find an AHCI controller ==
 
An AHCI controller can be found by enumerating the PCI bus. It has a class id 0x01 (mass storage device) and normally a subclass id 0x06 (serial ATA, but can be IDE Interface 0x01). The vendor id and device id should also be checked to ensure it’s really an AHCI controller.
 
=== Determining what mode the controller is in ===
As you may be aware, a SATA controller can either be in IDE emulation mode or in AHCI mode. The problem that enters here is simple: <br />
'''How to find what mode the controller is in'''. The documentation is really obscure on this. Perhaps the best way is to initialize a SATA controller as both IDE and AHCI. In this way, as long as you are careful about non-existent ports, you cannot go wrong.
 
One possible way of doing this is by checking the bit 31 of GHC register. It's labeled as AHCI Enable.
 
== AHCI Registers and Memory Structures ==
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[[Image:HBA_registers.jpg‎]]
 
<sourcesyntaxhighlight lang="c">
typedef volatile struct tagHBA_MEM
{
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uint32_t vendor[4]; // 0x70 ~ 0x7F, vendor specific
} HBA_PORT;
</syntaxhighlight>
</source>
 
This memory area should be configured as uncacheable as they are memory mapped hardware registers, not normal prefetchable RAM. For the same reason, the data structures are declared as "volatile" to prevent the compiler from over optimizing the code.
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Data FIS – Device to Host is not copied to this structure. Data payload is sent and received through PRDT (Physical Region Descriptor Table) in Command List, as will be introduced later.
 
<sourcesyntaxhighlight lang="c">
typedef volatile struct tagHBA_FIS
{
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uint8_t rsv[0x100-0xA0];
} HBA_FIS;
</syntaxhighlight>
</source>
 
'''4) Command List'''
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[[Image:Command_list.jpg‎]]
 
<sourcesyntaxhighlight lang="c">
typedef struct tagHBA_CMD_HEADER
{
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uint32_t rsv1[4]; // Reserved
} HBA_CMD_HEADER;
</syntaxhighlight>
</source>
 
'''5) Command Table and Physical Region Descriptor Table'''
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[[Image:Command_table.jpg‎]]
 
<sourcesyntaxhighlight lang="c">
typedef struct tagHBA_CMD_TBL
{
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uint32_t i:1; // Interrupt on completion
} HBA_PRDT_ENTRY;
</syntaxhighlight>
</source>
 
== Detect attached SATA devices ==
 
'''1) Which port ishas a device attached'''
 
As specified in the AHCI specification, firmware (BIOS) should initialize the AHCI controller into a minimal workable state. OS usually needn’t reinitialize it from the bottom. Much information is already there when the OS boots.
 
The Port Implemented register (HBA_MEM.pi) is a 32 bit value and each bit represents a port. If the bit is set in this register, then the accordingcorresponding port hasis present (note: this does not necessarily mean a device is attached, otherwiseto the port). A device is attached to a port if the value of the port's HBA_PxSSTS.det field is free0x3.
 
'''2) What kind of device is attached'''
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There are four kinds of SATA devices, and their signatures are defined as below. The Port Signature register (HBA_PORT.sig) contains the device signature, just read this register to find which kind of device is attached at the port. Some buggy AHCI controllers may not set the Signature register correctly. The most reliable way is to judge from the Identify data read back from the device.
 
<sourcesyntaxhighlight lang="c">
#define SATA_SIG_ATA 0x00000101 // SATA drive
#define SATA_SIG_ATAPI 0xEB140101 // SATAPI drive
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}
}
</syntaxhighlight>
</source>
 
== AHCI port memory space initialization ==
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Before rebasing Port memory space, OS must wait for current pending commands to finish and tell HBA to stop receiving FIS from the port. Otherwise an accidently incoming FIS may be written into a partially configured memory area. This is done by checking and setting corresponding bits at the Port Command And Status register (HBA_PORT.cmd). The example subroutines stop_cmd() and start_cmd() do the job.
 
The following example assumes that the HBA has 32 ports implemented and each port contains 32 command slots, and will allocate 8 PRDTs for each command slot. (Note: unlike in the above struct definitions, this is using 8 instead of 1)
 
<sourcesyntaxhighlight lang="c">
#define AHCI_BASE 0x400000 // 4M
 
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// Clear ST (bit0)
port->cmd &= ~HBA_PxCMD_ST;
 
// Clear FRE (bit4)▼
port->cmd &= ~HBA_PxCMD_FRE;▼
 
// Wait until FR (bit14), CR (bit15) are cleared
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}
 
▲ // Clear FRE (bit4)
▲ port->cmd &= ~HBA_PxCMD_FRE;
}
</syntaxhighlight>
</source>
 
== AHCI & ATAPI ==
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The code example shows how to read "count" sectors from sector offset "starth:startl" to "buf" with LBA48 mode from HBA "port". Every PRDT entry contains 8K bytes data payload at most.
 
<sourcesyntaxhighlight lang="c">
#define ATA_DEV_BUSY 0x80
#define ATA_DEV_DRQ 0x08
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{
// If not set in SACT and CI, the slot is free
uint32_t slots = (m_portport->sact | m_portport->ci);
for (int i=0; i<cmdslots; i++)
{
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return -1;
}
</syntaxhighlight>
</source>
 
== Checklist ==
 
=== Initialisation ===
 
* Enable interrupts, DMA, and memory space access in the PCI command register
* Memory map BAR 5 register as uncacheable.
* Perform BIOS/OS handoff (if the bit in the extended capabilities is set)
* Reset controller
* Register IRQ handler, using interrupt line given in the PCI register. This interrupt line may be shared with other devices, so the usual implications of this apply.
* Enable AHCI mode and interrupts in global host control register.
* Read capabilities registers. Check 64-bit DMA is supported if you need it.
* For all the implemented ports:
** Allocate physical memory for its command list, the received FIS, and its command tables. Make sure the command tables are 128 byte aligned.
** Memory map these as uncacheable.
** Set command list and received FIS address registers (and upper registers, if supported).
** Setup command list entries to point to the corresponding command table.
** Reset the port.
** Start command list processing with the port's command register.
** Enable interrupts for the port. The D2H bit will signal completed commands.
** Read signature/status of the port to see if it connected to a drive.
** Send IDENTIFY ATA command to connected drives. Get their sector size and count.
 
=== Start read/write command ===
 
* Select an available command slot to use.
* Setup command FIS.
* Setup PRDT.
* Setup command list entry.
* Issue the command, and record separately that you have issued it.
 
=== IRQ handler ===
 
* Check global interrupt status. Write back its value. For all the ports that have a corresponding set bit...
* Check the port interrupt status. Write back its value. If zero, continue to the next port.
* If error bit set, reset port/retry commands as necessary.
* Compare issued commands register to the commands you have recorded as issuing. For any bits where a command was issued but is no longer running, this means that the command has completed.
* Once done, continue checking if any other devices sharing the IRQ also need servicing.
 
== External Links ==
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*[https://github.com/omarrx024/xos/blob/master/kernel/blkdev/ahci.asm xOS AHCI implementation (assembly language)]
*[https://github.com/rajesh5310/SBUnix/blob/master/sys/ahci.c SBUnix implementation]
 
[[Category:ATA]]
[[Category:Storage]]
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